1. Field of the invention
The present invention relates to apparatus for digital alarm signal gathering and reconfiguration signal transmission in a communication system which has a function of gathering digital alarm signal which is needed for checking the state inside of the system and allocating reference address to such component as PLD (Programmable Logic Device) which needs a reconfiguration function.
The present invention was supported by the IT R&D program of Ministry of Information and Communication (MIC) and Institute for Information Technology Advancement (IITA) [Project reference number: 2007-S-014-01, Title of the Project: Metro-Access Integrated Optical Network Technology].
2. Description of the Related Art
Generally, when detecting the occurrence of digital alarm signals, an alarm signal gathering apparatus gathers and transmits the digital alarm signals to an integrated controller through a parallel bus.
In case the digital alarm signals which are to be collected outnumber the digital alarm signals which can be gathered by the alarm signal gathering apparatus, a plurality of alarm signal gathering apparatuses are connected to a single parallel bus.
FIG. 1 shows a block-diagram which illustrates the constitution of a general digital alarm signal gathering apparatus.
Referring to FIG. 1, in case digital alarm signal 1 exists, the digital alarm signal gathering apparatus 5 gathers and transmits the digital alarm signal to an integrated controller (not shown in the figure) through a parallel bus 10.
FIG. 2 shows a block-diagram which illustrates the constitution of general digital alarm signal gathering apparatus in case the 1st to the nth digital alarm signals exist.
Referring to FIG. 2, in case the 1st to the nth digital alarm signals 15 exist, an address decoding gathering apparatus 20 collects the 1st to the nth digital alarm signals 15a, 15b, . . . 15n according to its respective address which is allocated to the 1st to the nth digital alarm signals, respectively, and transmits them to an integrated controller (not shown in the figure) through a parallel bus 10.
In case the digital alarm signals 15 which are to be collected outnumber the digital alarm signals which can be gathered by the address decoding gathering apparatus 20, a plurality of address decoding gathering apparatuses may be connected to a single parallel bus. However, as compared with a serial bus connection structure where a single bus is serially connected to a plurality of decoding gathering apparatuses 20 so that single input and single output may be transmitted to the decoding gathering apparatuses, in a parallel bus connection structure where a single bus is parallel connected to a plurality of decoding gathering apparatuses 20 so that input and output to the decoding gathering apparatuses may be shared, signal integrity of the parallel data transmission line has to be secured in the course of circuit design or printed circuit board design for the sharing of a single bus due to limited electrical drive strength, the number of components wholly needed increases because the components related to the parallel bus buffering are to be added, and thus the necessary area is to be increased. Further, a difficulty follows that gathering software is to be additionally developed for the respective address decoding gathering apparatus 20.
Still further, to reconfigure the components such as reconfigurable and internally modifiable PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array) in a unit of the blocks or modules during the operation of the communication system, such inconvenience takes place as entire system is to be put to stop or the corresponding blocks or modules are to be pulled out and reconfigured in another working place.